José Peralta¹   Gabriela Peretti¹   Eduardo Romero^1,2   Carlos Marqués²

1 Grupo de Investigación y Servicios en Electrónica y Control. Facultad Regional Villa María. Universidad Tecnológica Nacional. Avda . Universidad 450, (5900) Villa María. Argentina. E-mail: gisec@frvm.utn.edu.ar

2 Grupo de Desarrollo Electrónico e Instrumental. Facultad de Matemática, Astronomía y Física, Universidad Nacional de Córdoba. Medina Allende y Haya de Torre, (5000). Córdoba, Argentina. E-mail: marques@famaf.unc.edu.ar

RESUMEN

En este trabajo se evalúa la capacidad de la estrategia de test denominada Método de Análisis de Transitorio para la detección de fallas paramétricas . Estas fallas son definidas como violaciones en las especificaciones de un circuito debido a desviaciones estadísticas en los componentes. Consecuentemente, el circuito es declarado como defectuoso si al menos una de las especificaciones está más allá de los límites tolerables. Un filtro de segundo orden se adopta como caso de estudio para la realización de las evaluaciones propuestas. Las especificaciones son establecidas sobre los parámetros de desempeño y los atributos de test son el tiempo de pico y la sobre elongación de la respuesta transitoria.

Para determinar la calidad del test , son generadas 8 poblaciones de 1.000 individuos. Cada individuo es obtenido asignando un valor aleatorio para sus componentes. Las poblaciones son obtenidas mediante el incremento de la variabilidad de los componentes, desde 3% hasta 10% en pasos de 1%. La evaluación concurrente de las especificaciones y de los parámetros de test permite establecer las métricas utilizadas para calificar al test. Los resultados de simulación permiten concluir que mediante la medición de los atributos de test propuestos es posible lograr un alto número de buenas decisiones de test . Adicionalmente, es posible observar que la capacidad de detección de circuitos buenos es también elevada. A pesar de estos hechos, el número de circuitos defectuosos que pasan el test podría ser inaceptable para aplicaciones que demanden una alta cobertura de fallas.

Palabras clave: Test de circuitos analógicos, método de análisis transitorio, detección de fallas paramétricas , detección de fallas de desviación.

ABSTRACT

In this work, the ability of the test strategy named Transient Analysis Method for detecting parametric faults is evaluated. These faults are defined as violations in the circuit specifications due to statistical deviations in the components. Consequently, a circuit is declared as faulty if at least one of the specifications is beyond the tolerable limits. A second order filter is adopted as a case study for performing the proposed evaluations. The specifications are established on performance parameters, and the test attributes are the peak time and the overshoot of the filter transient response.

In order to determine the test quality, 8 populations of 1.000 individuals are generated. Each individual is obtained by assigning a random value for its components. The populations are obtained by increasing the component variability from 3% up to 10% of their nominal values, in steps of 1%. The concurrent evaluation of the specifications and the test parameters allow establishing the metrics used for qualifying the test. The simulation results allow concluding that by the measuring of the proposed test attributes it is possible to achieve a high number of good test decisions. Additionally, it is possible to observe that the ability for detecting good circuits is also high. Despite these facts, the number of bad circuits passing the test could be unacceptable for applications demanding high fault coverage.

Keywords: Analog circuits test, transient analysis method, parametric fault detection, deviation fault detection.

REFERENCIAS

[1] B. Vinnakota (Editor). "Analog and Mixed-Signal Test". Prentice Hall. New York , United States . 1998. 

[2] A. Chatterjee , N. Nagi . "Design for testability and built-in self-test of mixed-signal circuits". Proceedings 10^th International Conference on VLSI Design, pp. 388-392. January 1997.

[3] M. Soma. "A design-for-test methodology for active analog filters". Proceedings IEEE International Test Conference, pp. 183-192. September 1990.

[4] D. Vázquez, A. Rueda, J. Huertas. "A new strategy for testing analog filters". IEEE VLSI Test Symposium, pp. 36-41. April 1994.

[5] K. Arabi , B. Kaminska . "Oscillation-test methodology for low-cost testing of active analog filters". IEEE Transactions on Instrumentation and Measurement. Vol. 48 N^o 4, pp. 798-806. August 1999.

[6] E. Romero, G. Peretti , G. Huertas, D. Vázquez. "Test of switched-capacitor ladder filters using OBT". Microelectronics Journal. Vol. 36 N^o 12, pp. 1073-1079. December 2005.

[7] J. L. Catalano, G. Peretti, E. Romero, C. Marqués. "Exploring the ability of oscillation based test for testing continuous-time ladder filters". Proceedings of the 7th International Symposium on Quality of Electronic Design, pp. 543-550. April 2006.

[8] J. Calvano , V. Alves, M. Lubaszeswski . "Fault detection methodology for second order filters using compact test vectors transient analysis". 3^rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 18-24. July 1999.

[9] J. Calvano , V. Alves, M. Lubaszeswski . "Fault detection methodology and BIST method for 2^nd order Butterworth, Chebyshev and Bessel Approximations." Proceedings of the 18^th IEEE VLSI Test Symposium, pp. 319-324. April 2000.

[10] J. Calvano, V. Alves, M. Lubaszeswski. "Designing for test analog signal processors for MEMS-based inertial sensors". Proceedings of the 3^rd IEEE International Workshop on System on Chip for Real Time Applications, pp. 251-256. June 2003. 

[11] K. Saab, N. Ben-Hamida, B. Kaminska. "Parametric fault simulation and test vector generation". Proceedings of the Conference on Design, Automation and Test in Europe , pp. 650-656. March 2000.

[12] A. Khouas , A. Derieux . "Fault simulation for analog circuits under parameter variations". Journal of Electronic Testing: Theory and Applications. Vol. 16 N^o 3, pp. 269-278. October 2000.

[13] S. Chang , C. Lee, J. Chen. "Structural fault based specification reduction for testing analog circuits". Journal of Electronic Testing. Vol. 18. N^o 6, pp. 571-581. December 2002.

[14] J. Savir , Z. Guo . "On the detectability of parametric faults in analog circuits". Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 273-276. September 2002.

[15] J. Savir , Z. Guo . "Analog circuit test using transfer function coefficient estimates". Proceedings of the IEEE International Test Conference. Vol. 1, pp. 1155-1163. September 2003.

[16] J. Savir , Z. Guo . "Test limitations of parametric faults in analog circuits". IEEE Transactions on Instrumentation and Measurement. Vol. 52 N^o 5, pp. 1444-1454. October 2003.

[17] E. Acar , S. Ozev . "Parametric test development for RF circuits targeting physical faults locations and using specification-based fault definitions". IEEE-ACM. International Conference on Computer Aided Design, pp. 73-79. November 2005.

[18] F. Liu, S. Ozev . "Fast hierarchical process variability analysis and parametric test development for analog/RF circuits". Proceedings of the International Conference on Computer Design, pp. 161-170. October 2005.

[19] A. Raghunathan , J. Chun y J. Abraham. "Quasi-oscillation based test for improved prediction of analog performance parameters". Proceedings of the International Test Conference, pp. 252-261. September 2004.

[20] A. Chaehoi , Y. Bertrand, L. Latorre , P. Nouet . "Improving the efficiency of the oscillation based test methodology for parametric faults". IEEE Latin American Test Workshop, pp. 234-237. March 2003.

[21] A. Chaehoi, L. Latorre, F. Azais, P. Nouet. "Use of a statistical approach for efficient implementation of oscillation based test strategy". Proceedings of the 9^th International Mixed Signal Test Workshop, pp. 99-103. June 2003.

[22] B. Kaminska , K. Arabi , I. Bell, P. Goteti , J. Huertas , B. Kim, A. Rueda , M. Soma. "Analog and mixed-signal benchmark circuits-First release". Proceedings of the International Test Conference, pp. 183-190. November 1997.